Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 559 of 1513
Aug 12, 2011
Figure 9-56. Encoder Compare Mode Operation Processing
Count up
16-bit counter cleared
and started.
INTTT0CC0 signal generated.
16-bit counter cleared
and started.
16-bit counter cleared
and started.
INTTIEC0 signal generated.
TT0ECM0 = 1?
(TT0CTL2)
Yes
No
TECR0 edge detected?
Yes
No
Clear level condition of
TENC00, TENC01, and TECR0
pins detected?
Yes
A
A
No
TT0SCE = 1?
(TT0IOC3)
Yes
No
Count value matches
CCR0 register value?
Yes
No No
16-bit counter cleared
and started.
INTTT0CC1 signal generated.
TT0CCR0 set value
transferred to 16-bit counter.
INTTT0CC0 signal generated.
Valid edge of TENC00,
TENC01 detected?
Yes
No
Which count operation?
Count down
TT0ECM1 = 1?
(TT0CTL2)
Yes
No
Yes
TT0LDE = 1?
(TT0CTL2)
Yes
No
Underflow?
Yes
No
Count value matches
CCR1 register value?