Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 558 of 1513
Aug 12, 2011
9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)
In the encoder compare mode, the encoder is controlled by using both the TT0CCR0 and TT0CCR1 registers as
compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0).
In this mode, the 16-bit counter can be cleared to 0000H in three ways: when the count value of the counter matches
the value of the CCRn buffer register (compare match interrupt request signal (INTTT0CCn) is generated), when the edge
of the encoder clear input (TECR0 pin) is detected, and when the clear level condition of TENC00, TENC01, and TECR0
pins is detected.
When the 16-bit counter underflows, the set value of the TT0CCR0 register can be transferred to the counter.
(1) Encoder compare mode operation flow
Figure 9-55. Encoder Compare Mode Operation Flow
TT0CE bit = 1
TT0CE bit = 0
Encoder compare mode operation processing
Register initial setting
TT0CTL1 register
(TT0MD3 to TT0MD0 bits),
TT0CTL2 register
(TT0LDE, TT0ECM1, TT0ECM0,
TT0UDS1, TT0UDS0 bits),
TT0IOC3 register
(TT0SCE, TT0ZCL, TT0ACL,
TT0BCL, TT0ECS1, TT0ECS0,
TT0EIS1, TT0EIS0 bits),
TT0CCR0, TT0CCR1 registers,
TT0TCW register
START
END
Operation end?
Yes
No
: See Figure 9-56 Encoder Compare Mode Operation Processing.