Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 557 of 1513
Aug 12, 2011
(b) If overflow does not occur immediately after start of operation
If the count operation is resumed when the TT0CTL2.TT0ECC bit = 1, the 16-bit counter does not overflow if its
count value that has been held is FFFFH and if the next count operation is counting up.
After the counter starts operating and counts up from a count value (value of TT0TCW register = FFFFH), the
counter overflows from FFFFH to 0000H. However, detection of the overflow is masked, the overflow flag
(TT0EOF) is not set, and the overflow interrupt request signal (INTTT0OV) is not generated.
TT0ECC bit
TT0CNT register
TT0TCW register
INTTT0OV signal
TT0EOF bit
Count clock
TT0CE bit
Peripheral clock
Count
timing signal
Count
up/down signal
0000HFFFFH
L = Count up
Hold
H
TT0TCW = FFFFH
FFFFH
Overflow does
not occur.