Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 556 of 1513

Aug 12, 2011

(7) Notes on using encoder count function

(a) If compare match interrupt is not generated immediately after operation is started

If a value which is the same as that of the TT0TCW register is set to the TT0CCR0 or TT0CCR1 register and

the counter operation is started when the TT0CTL2.TT0ECC bit = 0, and if the count value (TT0TCW) of the

16-bit counter matches the value of the CCRn buffer register immediately after the start of the operation, the

match is masked and the compare match interrupt request signal (INTTT0CCn) is not generated (n = 0, 1). In

addition, the 16-bit counter is not cleared to 0000H by setting the TT0CTL2.TT0ECM1 and

TT0CTL2.TT0ECM0 bits.

TT0CNT register

TT0CCR1 register

INTTT0CC1 signal

Count clock

TT0CE bit

Peripheral clock

Count

timing signal

Count

up/down signal

TT0TCW − 1FFFFH

H = Count down

TT0TCW

Match does not occur.

16-bit counter is not cleared.