Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 554 of 1513
Aug 12, 2011
Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and
TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (2/3)
(ii) If the high level is input to the TECR0 pin at the same time as the low level is input to the TECN01 pin
while the counter is counting up, the counter is cleared without counting up.
Peripheral clock
Clear signal
TT0CNT register
Encoder input
(TENC00 pin input)
Encoder input
(TENC01 pin input)
Encoder clear input
(TECR0 pin input)
Count
timing signal
0000HN
H
L
H
(iii) If the high level is input to the TECR0 pin earlier than the low level is input to the TENC01 pin while
the counter is counting up, the counter is cleared without counting up.
Peripheral clock
Clear signal
TT0CNT register
Encoder input
(TENC00 pin input)
Encoder input
(TENC01 pin input)
Encoder clear input
(TECR0 pin input)
Count
timing signal
0000HN
H
L
H