Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 553 of 1513

Aug 12, 2011

Figure 9-54. Operation Example (When TT0SCE Bit = 1, TT0ZCL Bit = 1, TT0BCL Bit = 0, TT0ACL Bit = 1, TT0UDS1 and

TT0UDS0 Bits = 11, TECR0 = High Level, TENC01 = Low Level, and TENC00 = High Level) (1/3)

(i) If inputting the high level to the TECR0 pin lags behind inputting the low level to the TENC01 pin

while the counter is counting up, the counter is cleared after it counts up.

Peripheral clock

Clear signal

TT0CNT register

TT0CCR0 register

INTTT0CC0 signal

TT0CCR1 register

INTTT0CC1 signal

TT0CCR0 register

INTTT0CC0 signal

Encoder input

(TENC00 pin input)

Encoder input

(TENC01 pin input)

Encoder clear input

(TECR0 pin input)

Count timing

signal

N + 1N

Compare match interrupt request signal is not generated.

0000H

N + 1 (when TT0CCR0 register is set to N + 1)

N (when TT0CCR0 register is set to N)

0000H (when TT0CCR1 register is set to 0000H)