Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 552 of 1513
Aug 12, 2011
(b) Clearing method <2>: By detecting clear level condition of the TENC00, TENC01, and TECR0 pins
(TT0SCE bit = 1)
When the TT0SCE bit = 1, the 16-bit counter is cleared to 0000H if the clear level condition of the TECR0,
TENC00, or TENC01 pin specified by the TT0ZCL, TT0BCL, and TT0ACL bits is detected. At this time, the
encoder clear interrupt request signal (INTTT0EC) is not generated. The settings of the TT0ECS1 and
TT0ECS0 bits is invalid when the TT0SCE bit = 1.
Table 9-10. 16-bit Counter Clearing Condition When TT0SCE Bit = 1
Clear Level Condition Setting Input Level of Encoder Pin
TT0ZCL Bit TT0BCL Bit TT0ACL Bit TECR0 Pin TENC01 Pin TENC00 Pin
0 0 0 L L L
0 0 1 L L H
0 1 0 L H L
0 1 1 L H H
1 0 0 H L L
1 0 1 H L H
1 1 0 H H L
1 1 1 H H H
Caution The 16-bit counter is cleared to 0000H when the clear level condition of the TT0ZCL, TT0BCL, and
TT0ACL bits match the input level of the TECR0, TENC01, or TENC00 pin.