Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 551 of 1513
Aug 12, 2011
(6) Function to clear counter to 0000H by encoder clear signal (TECR0 pin)
The 16-bit counter can be cleared to 0000H by the input signal of the TECR0 pin in two ways which are selected by
the TT0IOC3.TT0SCE bit. The TT0SCE bit also controls, depending on its setting, the TT0IOC3.TT0ZCL,
TT0IOC3.TT0BCL, TT0IOC3.TT0ACL, TT0IOC3.TT0ESC1, and TT0IOC3.TT0ECS0 bits.
The counter can be cleared by the methods described below only in the encoder compare mode.
Table 9-9. Relationship Between TT0SCE Bit and TT0ZCL, TT0BCL, TT0ACL, TT0ECS1, and TT0ECS0 Bits
Clearing Method TT0SCE Bit TT0ZCL Bit TT0BCL Bit TT0ACL Bit TT0ECS1, TT0ECS0 Bits
<1> 0 Invalid Invalid Invalid Valid
<2> 1 Valid Valid Valid Invalid
(a) Clearing method <1>: By detecting edge of encoder clear signal (TECR0 pin) (TT0SCE bit = 0)
When the TT0SCE bit = 0, the 16-bit counter is cleared to 0000H in synchronization with the peripheral clock if
the valid edge of the TECR0 pin specified by the TT0ECS1 and TT0ECS0 bits is detected. At this time, an
encoder clear interrupt request signal (INTTT0EC) is generated. When the TT0SCE bit = 0, the settings of the
TT0ZCL, TT0BCL, and TT0ACL bits is invalid.
Figure 9-53. Operation Example (When TT0SCE Bit = 0, TT0ECS1 and TT0ECS0 Bits = 01, and TT0UDS1 and
TT0UDS0 Bits = 11)
Peripheral clock
TT0CNT register
Encoder input
(TENC00 pin input)
Encoder input
(TENC01 pin input)
Encoder clear input
(TECR0 pin input)
Count
timing signal
N + 1N
Counter clear
0000H 0001H 0002H
INTTT0EC
interrupt