Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 547 of 1513
Aug 12, 2011
• When TT0UDS1 and TT0UDS0 bits = 11
TENC00 Pin TENC01 Pin Count Operation
Low level Falling edge
Rising edge Low level
High level Rising edge
Falling edge
Count down
Rising edge
High level
High level Falling edge
Falling edge Low level
Low level Rising edge
Count up
Simultaneous input to TENC00 and TENC01 pins
Counter does not perform count
operation but holds value immediately
before.
Caution Specification of the valid edges of the TENC00 and TENC01 pins is invalid.
Figure 9-49. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins do not Overlap)
Count up
TENC00
TENC01
16-bit counter
0004H0003H 0006H0005H 0008H0007H 000AH0009H 0008H0009H 0006H0007H 0005H
Count down
Figure 9-50. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins Overlap)
Count up Count up Count
up
Value
held
Value
held
TENC00
TENC01
16-bit counter
0004H0003H 0005H 0008H0007H 0006H0007H 0006H 0006H 0005H
Count down