Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 546 of 1513
Aug 12, 2011
• When TT0UDS1 and TT0UDS0 bits = 10
TENC00 Pin TENC01 Pin Count Operation
Low level Falling edge Counter does not perform count
operation but holds value immediately
before.
Rising edge Low level Count down
High level Rising edge
Falling edge
Rising edge
High level
High level Falling edge
Counter does not perform count
operation but holds value immediately
before.
Falling edge Low level Count up
Low level
Rising edge
Falling edge
Rising edge Counter does not perform count
operation but holds value immediately
before.
Rising edge Count down
Falling edge
Falling edge
Count up
Caution Specification of the valid edges of the TENC00 and TENC01 pins is invalid.
Figure 9-47. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins do not Overlap)
0007H
TENC00
TENC01
16-bit counter 0006H
Count down
Count
up
Count
down
Count
up
Count
down
Count up
0005H 0006H 0005H 0005H0006H 0006H 0007H
Figure 9-48. Operation Example (Count Operation When Valid Edges of TENC00 and TENC01 Pins Overlap)
0007H
TENC00
TENC01
16-bit counter 0006H
Count down Value held
Count
down
Count up
0005H 0006H 0007H