Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 545 of 1513
Aug 12, 2011
• When TT0UDS1 and TT0UDS0 bits = 01
TENC00 Pin TENC01 Pin Count Operation
Rising edge
Falling edge
Low level
Both edges
Rising edge
Falling edge
High level
Both edges
Count down
Rising edge
Falling edge
Both edges
High level
Rising edge
Falling edge
Both edges
Low level
Count up
Simultaneous input to TENC00 and TENC01 pins
Counter does not perform count
operation but holds value immediately
before.
Remark Detecting the edges of the TENC00 and TENC01 pins is specified by the
TT0IOC3.TT0EIS1 and TT0IOC3.TT0EIS0 bits.
Figure 9-46. Operation Example (When Rising Edge Is Specified as Valid Edges of TENC00 and TENC01 Pins)
0006H
TENC00
TENC01
16-bit counter 0007H 0008H
Count up
Value held Count down
0007H 0006H 0005H