Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 544 of 1513
Aug 12, 2011
(b) Detailed explanation of each bit
<1> TT0UDS1 and TT0UDS0 bits: Count-up/-down selection
Whether the 16-bit counter is counting up or down is identified by the phase input from the TENC00 or
TENC01 pin and depending on the settings of the TT0UDS1 and TT0UDS0 bits. These bits are valid
only in the encoder compare mode.
• When TT0UDS1 and TT0UDS0 bits = 00
TENC00 Pin TENC01 Pin Count Operation
Rising edge
Falling edge
Both edges
High level Count down
Rising edge
Falling edge
Both edges
Low level Count up
Remark Detecting the edge of the TENC00 pin is specified by the TT0IOC3.TT0EIS1 and TT0EIS0
bits.
Figure 9-45. Operation Example (When Valid Edge of TENC00 Pin Is Specified to Be Rising Edge
and No Edge Is Specified as Valid Edge of TENC01 Pin)
0007H
TENC00
TENC01
16-bit counter 0006H
Count down Count up
0005H 0004H 0005H 0006H 0007H