Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 543 of 1513
Aug 12, 2011
(5) Controlling bits of TT0CTL2 register
The setting of the TT0CTL2 register in the encoder compare mode is shown below.
Table 9-8. Setting of TT0CTL2 Register
Mode
TT0UDS1,
TT0UDS0 Bits
(<1>)
TT0ECM1 Bit
(<2>)
TT0ECM0 Bit
(<2>)
TT0LDE Bit
(<3>)
Counter Clear
(Target Compare
Register)
Transfer to
Counter
0
−
0
1
−
Possible
0
−
0
1
1
TT0CCR0
Possible
Note
0 Invalid TT0CCR1
−
Encoder compare
mode
Can be set to 00,
01, 10, or 11.
1
1 Invalid
TT0CCR0,
TT0CCR1
−
Note The counter can operate in a range from 0000H to the set value of the TT0CCR0 register.
(a) Outline of each bit
<1> The TT0UDS1 and TT0UDS0 bits identify the counting direction (up or down) of the 16-bit counter by the
phase input from the encoder input pin (TENC00 or TENC01).
<2> The TT0ECM1 and TT0ECM0 bits control clearing of the 16-bit counter when its count value matches the
value of the CCR0 or CCR1 buffer register.
<3> The TT0LDE bit controls a function to transfer the set value of the TT0CCR0 register to the 16-bit counter
when the counter underflows. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits are 00
and 01, respectively. It is invalid when these bits are set to any other values.