Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 542 of 1513
Aug 12, 2011
9.6.9 Encoder count function
The encoder count function includes an encoder compare mode (see 9.6.10 Encoder compare mode (TT0MD3 to
TT0MD0 bits = 1000)).
Mode TT0CCR0 Register TT0CCR1 Register
Encoder compare mode Compare only Compare only
(1) Count-up/-down control
Counting up or down by the 16-bit counter is controlled by the phase of input encoder signals (TENC00 and
TENC01) and settings of the TT0CTL2.TT0UDS1 and TT0CTL2.TT0UDS0 bits.
When the encoder count function is used, the internal count clock and external event count input (EVTT0) cannot
be used. Set the TT0CTL0.TT0CKS2 to TT0CTL0.TT0CKS0 bits to 000 and the TT0CTL1.TT0EEE bit to 0.
(2) Setting initial value of 16-bit counter
The initial count value set to the TT0TCW register when the TT0CTL2.TT0ECC bit = 0 is transferred to the 16-bit
counter immediately after the counter starts its operation (TT0CTL0.TT0CE bit = 0 → 1), and the counter starts the
operation after it detects the valid edge of the encoder input signal (TENC00 or TENC01).
(3) Basic operation
The TT0CCRn register generates a compare match interrupt request signal (INTTT0CCn) when the count value of
the 16-bit counter matches the value of the CCRn buffer register.
(4) Clear operation
The 16-bit counter is cleared when the following conditions are satisfied in the encoder compare mode.
• When the value of the 16-bit counter matches the value of the compare register (the TT0CTL2.TT0ECM1 and
TT0CTL2.TT0ECM0 bits are set)
• When the edge of the encoder clear input signal (TECR0) is detected (the TT0ECS1 and TT0ECS0 bits are set
when the TT0IOC3.TT0SCE bit = 0)
• When the clear level condition of the TENC00, TENC01, and TECR0 pins is detected (the TT0ZCL, TT0BCL, and
TT0ACL bits are set when the TT0SCE bit = 1)
Remark n = 0, 1