Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 54 of 1513
Aug 12, 2011
CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/JG3-H and V850ES/JH3-H is based on RISC architecture and executes almost all instructions
with one clock by using a 5-stage pipeline.
3.1 Features
Minimum instruction execution time: 20.8 ns (operating with main clock (fXX) of 48 MHz: VDD = 2.85 to 3.6 V)
30.5
μ s (operating with subclock (fXT) of 32.768 kHz)
Memory space Program (physical address) space: 64 MB linear
Data (logical address) space: 4 GB linear
General-purpose registers: 32 bits × 32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1