Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 535 of 1513
Aug 12, 2011
Figure 9-40. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TT0CE bit
TIT0n pin input
TT0CCRn register
INTTT0CCn signal
INTTT0OV signal
TT0OVF bit
D00000H D1 D2 D3
Cleared to 0 by
CLR instruction
Remark n = 0, 1
When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is later
detected, the count value of the 16-bit counter is stored in the TT0CCRn register, the 16-bit counter is cleared to 0000H,
and a capture interrupt request signal (INTTT0CCn) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value × Count clock cycle
If the valid edge is not input to the TIT0n pin even when the 16-bit counter counted up to FFFFH, an overflow interrupt
request signal (INTTT0OV) is generated at the next count clock, and the counter is cleared to 0000H and continues
counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Clear the overflow flag to 0 by executing
the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H × TT0OVF bit set (1) count + Captured value) × Count clock cycle
Remark n = 0, 1