Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 534 of 1513
Aug 12, 2011
9.6.7 Pulse width measurement mode (TT0MD3 to TT0MD0 bits = 0110)
In the pulse width measurement mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set
to 1. Each time the valid edge input to the TIT0n pin has been detected, the count value of the 16-bit counter is stored in
the TT0CCRn register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TT0CCRn register after a capture interrupt request
signal (INTTT0CCn) occurs.
As shown in Figure 9-39, select either the TIT00 or TIT01 pin as the capture trigger input pin and set the unused pins to
“No edge detection” by using the TT0IOC1 register.
Figure 9-39. Configuration in Pulse Width Measurement Mode
TT0CCR0 register
(capture)
TT0CE bit
TT0CCR1 register
(capture)
Edge
detector
Note 1
Count
clock
selection
Edge
detector
Note 2
Edge
detector
Note 3
EVTT0 pin
(external event
count input)
TIT00 pin
(capture
trigger input)
TIT01 pin
(capture
trigger input)
Internal count clock
Clear
INTTT0OV signal
INTTT0CC0 signal
INTTT0CC1 signal
16-bit counter
Notes 1. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
2. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits.
3. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits.