Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 533 of 1513
Aug 12, 2011
Example when capture trigger interval is long
FFFFH
16-bit counter
0000H
TT0CE bit
TIT0n pin input
TT0CCRn register
INTTT0OV signal
TT0OVF bit
Overflow
counter
Note
D a0 D a1
1H0H 2H 0H
D a0
D a1
<1> <2> <3> <4>
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TT0CCRn register (setting of the default value of the TIT0n pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the
overflow interrupt servicing.
<3> An overflow occurs a second time. Increment the overflow counter and clear the overflow flag to 0
in the overflow interrupt servicing.
<4> Read the TT0CCRn register.
Read the overflow counter.
→ When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D
a1 –
D
a0).
In this example, the pulse width is (20000H + D
a1 – Da0) because an overflow occurs twice.
Clear the overflow counter (0H).
Remark n = 0, 1
(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TT0OVF bit to 0 with the CLR instruction after reading the
TT0OVF bit when it is 1 and by writing 8-bit data (bit 0 is 0) to the TT0OPT0 register after reading the TT0OVF
bit when it is 1.