Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 527 of 1513
Aug 12, 2011
(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter T is used as an interval timer with the TT0CCRn register used as a compare
register, software processing is necessary for setting a comparison value to generate the next interrupt request
signal each time the INTTT0CCn signal has been detected.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
D 00 D 01 D 02 D 03 D 04 D 05
D 10
D 00
D 11
D 01
D 12
D 04
D 13
D 02
D 03
D 11 D 10 D 12 D 13 D 14
Interval period
(D
10 + 1)
Interval period
(10000H
+
D 11 − D 10 )
Interval period
(10000H
+
D 12 − D 11 )
Interval period
(10000H
+
D 13 − D 12 )
Interval period
(D
00 + 1)
Interval period
(10000H +
D
01 − D00)
Interval period
(D
02 − D01)
Interval period
(10000H +
D
03 − D02)
Interval period
(10000H +
D
04 − D03)
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TT0CCRn register must be re-set in the
interrupt servicing that is executed when the INTTT0CCn signal is detected.
The set value for re-setting the TT0CCRn register can be calculated by the following expression, where “D
a” is
the interval period.
Compare register default value: D
a − 1
Value set to compare register second and subsequent time: Previous set value + D
a
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)