Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 524 of 1513

Aug 12, 2011

Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)

TT0CE bit = 1

Read TT0OPT0 register

(check overflow flag).

TT0CTL0 register

(TT0CKS0 to TT0CKS2 bits)

TT0CTL1 register,

TT0IOC0 register,

TT0IOC2 register,

TT0OPT0 register,

TT0CCR0 register,

TT0CCR1 register

Initial setting of these registers

is performed before setting the

TT0CE bit to 1.

The TT0CKS0 to TT0CKS2 bits

can be set at the same time

as when counting starts

(TT0CE bit = 1).

START

Execute instruction to clear

TT0OVF bit (CLR TT0OVF).

<1> Count operation start flow

<2> Overflow flag clear flow

TT0CE bit = 0

Counter is initialized and

counting is stopped by

clearing TT0CE bit to 0.

STOP

<3> Count operation stop flow

TT0OVF bit = 1

Yes