Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 523 of 1513
Aug 12, 2011
(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
D 00 D 01
D 10 D 11
D 00
D 10 D 10
D 11 D 11 D 11
D 00
D 01 D 01
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<1>
<2> <2> <2>
<3>
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
INTTT0OV signal
TT0OVF bit