Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 522 of 1513
Aug 12, 2011
Figure 9-36. Register Setting in Free-Running Timer Mode (2/2)
(e) TMT0 I/O control register 2 (TT0IOC2)
0 0 0 0 0/1
TT0IOC2
Select valid edge of
external event count
input (EVTT0 pin)
0/1 0 0
TT0EES0 TT0ETS1 TT0ETS0TT0EES1
(f) TMT0 option register 0 (TT0OPT0)
0 0 0/1 0/1 0
TT0OPT0
Overflow flag
Specifies if TT0CCR0
register functions as
capture or compare register
0: Compare register
1: Capture register
Specifies if TT0CCR1
register functions as
capture or compare register
0: Compare register
1: Capture register
0 0 0/1
TT0CCS0 TT0OVF TT0CCS1
(g) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(h) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
These registers function as capture registers or compare registers depending on the setting of the
TT0OPT0.TT0CCSn bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIT0n pin is detected.
When the registers function as compare registers and when D
a is set to the TT0CCRn register, the
INTTT0CCn signal is generated when the counter reaches (D
a + 1), and the output signals of the
TOT00 and TOT01 pins are inverted.
Remark n = 0, 1