Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 521 of 1513
Aug 12, 2011
Figure 9-36. Register Setting in Free-Running Timer Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
0/1 0 0 0 0
TT0CTL0
Select count clock
Note
0: Stops counting
1: Enables counting
0/1 0/1 0/1
TT0CKS2 TT0CKS1 TT0CKS0TT0CE
Note The setting is invalid when the TT0CTL1.TT0EEE bit = 1
(b) TMT0 control register 1 (TT0CTL1)
0 0 0/1 0 0
TT0CTL1
101
TT0MD2 TT0MD1 TT0MD0TT0EEETT0EST TT0MD3
0, 1, 0, 1:
Free-running timer mode
0: Operates with count
clock selected by
TT0CKS0 to TT0CKS2 bits
1: Counts on external
event count input signal
(c) TMT0 I/O control register 0 (TT0IOC0)
0 0 0 0 0/1
TT0IOC0
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output
level before count operation
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output
level before count operation
0: Low level
1: High level
0/1 0/1 0/1
TT0OE1 TT0OL0 TT0OE0TT0OL1
(d) TMT0 I/O control register 1 (TT0IOC1)
0 0 0 0 0/1
TT0IOC1
Select valid edge
of TIT00 pin input
Select valid edge
of TIT01 pin input
0/1 0/1 0/1
TT0IS2 TT0IS1 TT0IS0TT0IS3