Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 520 of 1513

Aug 12, 2011

• Capture operation

When the TT0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIT0n pin is

detected, the count value of the 16-bit counter is stored in the TT0CCRn register, and a capture interrupt request

signal (INTTT0CCn) is generated.

The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it

generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues

counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set

to 1 and then clear it to 0 by executing the CLR instruction via software.

Figure 9-35. Basic Timing in Free-Running Timer Mode (Capture Function)

FFFFH

16-bit counter

0000H

TT0CE bit

TIT00 pin input

TT0CCR0 register

INTTT0CC0 signal

TIT01 pin input

TT0CCR1 register

INTTT0CC1 signal

INTTT0OV signal

TT0OVF bit

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction