Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 519 of 1513

Aug 12, 2011

• Compare operation

When the TT0CE bit is set to 1, 16-bit timer/event counter T starts counting, and the output signal of the TOT0n pin is

inverted. When the count value of the 16-bit counter later matches the set value of the TT0CCRn register, a compare

match interrupt request signal (INTTT0CCn) is generated, and the output signal of the TOT0n pin is inverted.

The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it

generates an overflow interrupt request signal (INTTT0OV) at the next clock, is cleared to 0000H, and continues

counting. At this time, the overflow flag (TT0OPT0.TT0OVF bit) is also set to 1. Confirm that the overflow flag is set

to 1 and then clear it to 0 by executing the CLR instruction via software.

The TT0CCRn register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at

that time by anytime write, and compared with the count value.

Figure 9-34. Basic Timing in Free-Running Timer Mode (Compare Function)

FFFFH

16-bit counter

0000H

TT0CE bit

TT0CCR0 register

INTTT0CC0 signal

TOT00 pin output

TT0CCR1 register

INTTT0CC1 signal

TOT01 pin output

INTTT0OV signal

TT0OVF bit

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction

Cleared to 0 by

CLR instruction