Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 518 of 1513
Aug 12, 2011
9.6.6 Free-running timer mode (TT0MD3 to TT0MD0 bits = 0101)
In the free-running timer mode, 16-bit timer/event counter T starts counting when the TT0CTL0.TT0CE bit is set to 1. At
this time, the TT0CCR0 and TT0CCR1 registers can be used as compare registers or capture registers, depending on the
setting of the TT0OPT0.TT0CCS0 and TT0OPT0.TT0CCS1 bits.
Figure 9-33. Configuration in Free-Running Timer Mode
TT0CCR0 register
(capture)
TT0CE bit
TT0CCR1 register
(compare)
16-bit counter
TT0CCR1 register
(compare)
TT0CCR0 register
(capture)
Output
controller
TT0CCS0, TT0CCS1 bits
(capture/compare selection)
TOT00 pin
Note 1
output
Output
controller
TOT01 pin
Note 1
output
Edge
detector
Note 2
Count
clock
selection
Edge
detector
Note 3
Edge
detector
Note 4
EVTT0 pin
(external event
count input)
TIT00 pin
Note 1
(capture
trigger input)
TIT01 pin
Note 1
(capture
trigger input)
Internal count clock
0
1
0
1
INTTT0OV signal
INTTT0CC1 signal
INTTT0CC0 signal
Notes 1. Because the capture trigger input pins (TIT00, TIT01) and timer output pins (TOT00, TOT01)
are the same alternate-function pins, two functions cannot be used at the same time.
2. Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
3. Set by the TT0IOC1.TT0IS1 and TT0IOC1.TT0IS0 bits.
4. Set by the TT0IOC1.TT0IS3 and TT0IOC1.TT0IS2 bits.