Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 514 of 1513
Aug 12, 2011
Figure 9-32. Software Processing Flow in PWM Output Mode (2/2)
TT0CE bit = 1
Setting of TT0CCR0 register
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR0 register,
TT0CCR1 register
Initial setting of these
registers is performed
before setting the
TT0CE bit to 1.
The TT0CKS0 to
TT0CKS2 bits can be
set at the same time
as when counting is
enabled (TT0CE bit = 1).
Writing the same value
(same as preset value of
the TT0CCR1 register)
to the TT0CCR1 register
is necessary only when
the set cycle is changed.
When the counter is
cleared after setting,
the value of the TT0CCRn
register is transferred to the
CCRn buffer register.
START
Setting of TT0CCR1 register
<1> Count operation start flow
<2> TT0CCR0, TT0CCR1 register
setting change flow (cycle only)
Setting of TT0CCR0 register
When the counter is
cleared after setting,
the values of compare
register n are transferred
to the CCRn buffer register
in a batch.
Setting of TT0CCR1 register
<4> TT0CCR0, TT0CCR1 register
setting change flow (cycle and duty)
Only writing of the TT0CCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register n
is transferred to the CCRn
buffer register.
Setting of TT0CCR1 register
<3> TT0CCR0, TT0CCR1 register
setting change flow (duty only)
TT0CE bit = 0
Counting is stopped.
STOP
<5> Count operation stop flow
Remark n = 0, 1