Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 512 of 1513
Aug 12, 2011
Figure 9-31. Register Setting in PWM Output Mode (2/2)
(d) TMT0 I/O control register 2 (TT0IOC2)
0 0 0 0 0/1
TT0IOC2
Select valid edge
of external event
count input (EVTT0 pin).
0/1 0 0
TT0EES0 TT0ETS1 TT0ETS0TT0EES1
(e) TMT0 counter read buffer register (TT0CNT)
The value of the 16-bit counter can be read by reading the TT0CNT register.
(f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)
If D
0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D
0 + 1) × Count clock cycle
Active level width = D
1 × Count clock cycle
Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control
register 3 (TT0CTL3), TMT0 option register 0 (TT0OPT0), TMT0 option register 1
(TT0OPT1), and TMT0 counter write register (TT0TCW) are not used in the PWM output
mode.