Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 510 of 1513
Aug 12, 2011
Figure 9-30. Basic Timing in PWM Output Mode
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
CCR0 buffer register
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
CCR1 buffer register
INTTT0CC1 signal
TOT01 pin output
D10
D00
D00 D01
D00
D10 D11
D10 D11
D01
D10 D10
D00 D00 D11D11
D01 D01
Active period
(D
10)
Cycle
(D
00 + 1)
Inactive period
(D
00 - D10 + 1)
When the TT0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOT01 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TT0CCR1 register) × Count clock cycle
Cycle = (Set value of TT0CCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TT0CCR1 register)/(Set value of TT0CCR0 register + 1)
The PWM waveform can be changed by rewriting the TT0CCRn register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and the
16-bit counter is cleared to 0000H.
The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTT0CC1) is generated when the count value of the 16-bit counter matches the value of
the CCR1 buffer register.
The value set to the TT0CCRn register is transferred to the CCRn buffer register when the count value of the 16-bit
counter matches the value of the CCRn buffer register and the 16-bit counter is cleared to 0000H.
Remark n = 0, 1