Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 509 of 1513
Aug 12, 2011
9.6.5 PWM output mode (TT0MD3 to TT0MD0 bits = 0100)
In the PWM output mode, a PWM waveform is output from the TOT01 pin when the TT0CTL0.TT0CE bit is set to 1.
In addition, a square wave with the set value of the TT0CCR0 register + 1 as half its cycle is output from the TOT00 pin.
Figure 9-29. Configuration in PWM Output Mode
CCR0 buffer register
TT0CE bit
TT0CCR0 register
16-bit counter
TT0CCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTT0CC0 signal
Output
controller
(RS-FF)
Output
controller
TOT01 pin
INTTT0CC1 signal
TOT00 pin
Transfer
Transfer
S
R
Count
clock
selection
Internal count clock
EVTT0 pin
(external event
count input)
Edge
detector
Note
Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.