Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 508 of 1513
Aug 12, 2011
(b) Generation timing of compare match interrupt request signal (INTTT0CC1)
The generation timing of the INTTT0CC1 signal in the one-shot pulse output mode is different from
INTTT0CC1 signals in other modes; the INTTT0CC1 signal is generated when the count value of the 16-bit
counter matches the value of the TT0CCR1 register.
Count clock
16-bit counter
TT0CCR1 register
TOT01 pin output
INTTT0CC1 signal
D 1
D 1 − 2D 1 − 1D 1 D 1 + 1 D 1 + 2
Note
Note
Note The timing is actually delayed by one operating clock (f
XX).
Usually, the INTTT0CC1 signal is generated the next time the 16-bit counter counts up after its count value
matches the value of the TT0CCR1 register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the timing the output signal of the TOT01 pin changes.