Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 507 of 1513
Aug 12, 2011
(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TT0CCRn register
If the value of the TT0CCRn register is rewritten to a smaller value during counting, the 16-bit counter may
overflow. When an overflow may occur, stop counting and then change the set value.
Remark n = 0, 1
D 10 D 11
D 00 D 01
D 00
D 10 D 10 D 10 D 01
D 11
D 00 D 00
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
External trigger input
(EVTT0 pin input)
Delay
(D
10 )
Active level width
(D
00 − D 10 + 1)
Delay
(D
10 )
Active level width
(D
00 − D 10 + 1)
Delay
(10000H + D
11 )
Active level width
(D
01 − D 11 + 1)
When the TT0CCR0 register is rewritten from D
00 to D01 and the TT0CCR1 register from D10 to D11 where D00 >
D
01 and D10 > D11, if the TT0CCR1 register is rewritten when the count value of the 16-bit counter is greater
than D
11 and less than D10 and if the TT0CCR0 register is rewritten when the count value is greater than D01
and less than D
00, each set value is reflected as soon as the register has been rewritten and compared with the
count value. The counter counts up to FFFFH and then counts up again from 0000H. When the count value
matches D
11, the counter generates the INTTT0CC1 signal and asserts the TOT01 pin. When the count value
matches D
01, the counter generates the INTTT0CC0 signal, deasserts the TOT01 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.