Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 506 of 1513
Aug 12, 2011
(1) Operation flow in one-shot pulse output mode
Figure 9-28. Software Processing Flow in One-Shot Pulse Output Mode
<1> <2> <3>
START
STOP
D 10 D 11
D 00 D 01
D 00
D 10
D 11
D 01
Setting of TT0CCR0, TT0CCR1
registers
<2> TT0CCR0, TT0CCR1 register setting change flow
TT0CE bit = 1
TT0CE bit = 0
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR0 register,
TT0CCR1 register
Initial setting of these
registers is performed
before setting the
TT0CE bit to 1.
The TT0CKS0 to
TT0CKS2 bits can be
set at the same time
as when counting starts
(TT0CE bit = 1).
Trigger wait status
Count operation is stopped
<1> Count operation start flow <3> Count operation stop flow
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
External trigger input
(EVTT0 pin input)
As rewriting the
TT0CCRn register
immediately forwards
to the CCRn buffer
register, rewriting
immediately after
the generation of the
INTTT0CC0 signal
is recommended.
Remark n = 0, 1