Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 505 of 1513

Aug 12, 2011

Figure 9-27. Setting of Registers in One-Shot Pulse Output Mode (2/2)

(d) TMT0 I/O control register 2 (TT0IOC2)

00000

TT0IOC2

Select valid edge of external

trigger input (EVTT0 pin)

Note

0 0/1 0/1

TT0ETS1 TT0ETS0TT0EES1 TT0EES0

Note Set the valid edge selection of the unused alternate external input signals to “No edge

detection”.

(e) TMT0 counter read buffer register (TT0CNT)

The value of the 16-bit counter can be read by reading the TT0CNT register.

(f) TMT0 capture/compare registers 0 and 1 (TT0CCR0 and TT0CCR1)

If D

0 is set to the TT0CCR0 register and D1 to the TT0CCR1 register, the active level width and output

delay period of the one-shot pulse are as follows.

Active level width = (D

0 − D1 + 1) × Count clock cycle

Output delay period = D1 × Count clock cycle

Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 1 (TT0IOC1), TMT0 I/O control

and TMT0 counter write register (TT0TCW) are not used in the one-shot pulse output mode.