Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 503 of 1513
Aug 12, 2011
Figure 9-26. Basic Timing in One-Shot Pulse Output Mode
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
TOT00 pin output
TT0CCR1 register
INTTT0CC1 signal
TOT01 pin output
External trigger input
(EVTT0 pin input)
D 1
D 0
D 0
D 1 D 1 D 1
D 0 D 0
Delay
(D
1 )
Active
level width
(D
0 − D 1 + 1)
Delay
(D
1 )
Active
level width
(D
0 − D 1 + 1)
Delay
(D
1 )
Active
level width
(D
0 − D 1 + 1)
When the TT0CE bit is set to 1, 16-bit timer/event counter T waits for a trigger. When the trigger is generated, the 16-bit
counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOT01 pin. After the one-
shot pulse is output, the 16-bit counter is cleared to 0000H, stops counting, and waits for a trigger. When the trigger is
generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the one-shot pulse is
being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TT0CCR1 register) × Count clock cycle
Active level width = (Set value of TT0CCR0 register − Set value of TT0CCR1 register + 1) × Count clock cycle
The compare match interrupt request signal (INTTT0CC0) is generated the next time the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTT0CC1) is
generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
The valid edge of an external trigger input (EVTT0 pin) or setting the software trigger (TT0CTL1.TT0EST bit) to 1 is
used as the trigger.