Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 502 of 1513
Aug 12, 2011
9.6.4 One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011)
In the one-shot pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set
to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting,
and outputs a one-shot pulse from the TOT01 pin.
Instead of the external trigger input (EVTT0), a software trigger can also be generated to output the pulse. When the
software trigger is used, the TOT00 pin outputs the active level while the 16-bit counter is counting, and the inactive level
when the counter is stopped (waiting for a trigger).
Figure 9-25. Configuration in One-Shot Pulse Output Mode
CCR0 buffer register
TT0CE bit
TT0CCR0 register
16-bit counter
TT0CCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTT0CC0 signal
Output
controller
(RS-FF)
Output
controller
(RS-FF)
TOT01 pin
INTTT0CC1 signal
TOT00 pin
Count
clock
selection
Internal count clock
Count
start
control
Edge
detector
Note 2
Software trigger
generation
Edge
detector
Note 3
Transfer
Transfer
S
R
S
R
EVTT0 pin
Note 1
(external
trigger input/
external event
count input)
Notes 1. Because the external trigger input pin (EVTT0) and external event count input pin (EVTT0) are
the same alternate-function pin, the external trigger input pin (EVTT0) cannot be used.
2. Edge detector for external trigger input.
Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits.
3. Edge detector for external event count input.
Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.