Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 498 of 1513
Aug 12, 2011
To output a 100% waveform, set a value of (set value of TT0CCR0 register + 1) to the TT0CCR1 register. If the
set value of the TT0CCR0 register is FFFFH, 100% output cannot be produced.
D 0
D 0 + 1
D
0
D 0 + 1
D
0
D 0 + 1
D 0 0000FFFF 0000 D 0 00000001
Count clock
16-bit counter
TT0CE bit
TT0CCR0 register
TT0CCR1 register
INTTT0CC0 signal
INTTT0CC1 signal
TOT01 pin output
D
0 − 1D 0 − 1
External trigger input
(EVTT0 pin input)
Note Note
Note The timing is actually delayed by one operating clock (fXX).