Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 497 of 1513
Aug 12, 2011
(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TT0CCR1 register to 0000H. The 16-bit counter is cleared to 0000H and the
INTTT0CC0 and INTTT0CC1 signals are generated after a match between the count value of the 16-bit
counter and the value of the CCR0 buffer register.
Count clock
16-bit counter
TT0CE bit
TT0CCR0 register
TT0CCR1 register
INTTT0CC0 signal
INTTT0CC1 signal
TOT01 pin output
External trigger input
(EVTT0 pin input)
D 0
L
0000H
D
0
0000H
D
0
0000H
D 0 − 1D 0 0000FFFF 0000 D 0 − 1D 0 00000001
Note
Note
Note
Note
Note The timing is actually delayed by one operating clock (f
XX).