Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 489 of 1513
Aug 12, 2011
9.6.3 External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010)
In the external trigger pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit
is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts
counting, and outputs a PWM waveform from the TOT01 pin.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
trigger, a square wave that has the set value of the TT0CCR0 register + 1 as half its cycle can also be output from the
TOT00 pin.
Figure 9-21. Configuration in External Trigger Pulse Output Mode
CCR0 buffer register
TT0CE bit
TT0CCR0 register
16-bit counter
TT0CCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTT0CC0 signal
Output
controller
(RS-FF)
Output
controller
TOT01 pin
INTTT0CC1 signal
TOT00 pin
Count
clock
selection
Internal count clock
Count
start
control
Edge
detector
Note 2
Software trigger
generation
EVTT0 pin
Note 1
(external
trigger input/
external event
count input)
Edge
detector
Note 3
Transfer
Transfer
S
R
Notes 1. Since the external trigger input pin and external event count input pin are the same alternate-
function pin, the external event count input function cannot be used.
2. Edge detector for external trigger input.
Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits.
3. Edge detector for external event count input.
Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.