Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)

R01UH0042EJ0500 Rev.5.00 Page 487 of 1513

Aug 12, 2011

(e) Operation of TT0CCR1 register

Figure 9-18. Configuration of TT0CCR1 Register

CCR0 buffer registerTT0CE bit

TT0CCR0 register

16-bit counter

TT0CCR1 register

CCR1 buffer register

Clear

Match signal

INTTT0CC0 signal

INTTT0CC1 signal

Edge

detector

Note

EVTT0 pin

(external event

count input)

Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.

If the set value of the TT0CCR1 register is smaller than the set value of the TT0CCR0 register, the INTTT0CC1

signal is generated once per cycle.

Figure 9-19. Timing Chart When D

01 ≥ D11

FFFFH

16-bit counter

0000H

TT0CE bit

TT0CCR0 register

INTTT0CC0 signal

TT0CCR1 register

INTTT0CC1 signal