Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 485 of 1513
Aug 12, 2011
(c) Operation with TT0CCR0 set to FFFFH and TT0CCR1 register to 0000H
When the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time it has detected
the valid edge of the external event count signal. The counter is then cleared to 0000H in synchronization with
the next count-up timing and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit is not
set.
If the TT0CCR1 register is set to 0000H, the INTTT0CC1 signal is generated when the 16-bit counter is cleared
to 0000H.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
TT0CCR1 register
INTTT0CC1 signal
FFFFH
0000H