Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 484 of 1513
Aug 12, 2011
(2) Operation timing in external event count mode
(a) Operation if TT0CCR0 register is set to 0000H
When the TT0CCR0 register is set to 0000H, the 16-bit counter is repeatedly cleared to 0000H and generates
the INTTT0CC0 signal each time it has detected the valid edge of the external event count signal and its value
has matched that of the CCR0 buffer register.
The value of the 16-bit counter is always 0000H.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
0000H
INTTT0CC0 signal is generated each time the 16-bit
counter counts the valid edge of the external event count input.
(b) Operation if TT0CCR0 register is set to FFFFH
If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH each time the valid edge of
the external event count signal has been detected. The 16-bit counter is cleared to 0000H in synchronization
with the next count-up timing, and the INTTT0CC0 signal is generated. At this time, the TT0OPT0.TT0OVF bit
is not set.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal
FFFFH
External event
count: 10000H
External event
count: 10000H
External event
count: 10000H