Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 483 of 1513
Aug 12, 2011
(1) External event count mode operation flow
Figure 9-17. Software Processing Flow in External Event Count Mode
TT0CE bit = 1
TT0CE bit = 0
Register initial setting
TT0CTL1 register,
TT0IOC2 register,
TT0CCR0, TT0CCR1 registers
Initial setting of these registers
is performed before setting the
TT0CE bit to 1.
The counter is initialized and counting
is stopped by clearing the TT0CE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
D0
D0 D0 D0
<1> <2>
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
INTTT0CC0 signal