Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 482 of 1513
Aug 12, 2011
Figure 9-16. Register Setting for Operation in External Event Count Mode (2/2)
(f) TMT0 capture/compare register 1 (TT0CCR1)
The TT0CCR1 register is not used in the external event count mode. However, the set value of the
TT0CCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit counter
matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTT0CC1) is
generated.
When the TT0CCR1 register is not used, it is recommended to set its value to FFFFH. Also mask the
register by the interrupt mask flag (TT0CCIC1.TT0CCMK1).
Remark TMT0 control register 2 (TT0CTL2), TMT0 I/O control register 0 (TT0IOC0), TMT0 I/O control
register 1 (TT0IOC1), TMT0 I/O control register 3 (TT0IOC3), TMT0 option register 0
(TT0OPT0), TMT0 option register 1 (TT0OPT1), and TMT0 counter write register (TT0TCW) are
not used in the external event count mode.