Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 481 of 1513
Aug 12, 2011
When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
each time the valid edge of external event count input is detected. Additionally, the set value of the TT0CCR0 register is
transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, and a compare match interrupt request signal (INTTT0CC0) is generated.
The INTTT0CC0 signal is generated each time the valid edge of the external event count input has been detected
“value set to TT0CCR0 register + 1” times.
Figure 9-16. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMT0 control register 0 (TT0CTL0)
0/1 0 0 0 0
TT0CTL0
0: Stops counting
1: Enables counting
000
TT0CKS2 TT0CKS1 TT0CKS0TT0CE
(b) TMT0 control register 1 (TT0CTL1)
00000
TT0CTL1
0, 0, 0, 1:
External event count mode
001
TT0MD2TT0MD3 TT0MD1 TT0MD0TT0EEETT0EST
(c) TMT0 I/O control register 2 (TT0IOC2)
0 0 0 0 0/1
TT0IOC2
Select valid edge
of external event
count input (EVTT0 pin)
0/1 0 0
TT0EES0 TT0ETS1 TT0ETS0TT0EES1
(d) TMT0 counter read buffer register (TT0CNT)
The count value of the 16-bit counter can be read by reading the TT0CNT register.
(e) TMT0 capture/compare register 0 (TT0CCR0)
If the TT0CCR0 register is set to D
0, the count is cleared when the number of external events has reached
(D0 + 1) and the compare match interrupt request signal (INTTT0CC0) is generated.