Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 479 of 1513
Aug 12, 2011
9.6.2 External event count mode (TT0MD3 to TT0MD0 bits = 0001)
In the external event count mode, the valid edge of the external event count input (EVTT0) is counted when the
TT0CTL0.TT0CE bit is set to 1, and an interrupt request signal (INTTT0CC0) is generated each time the number of edges
set by the TT0CCR0 register have been counted. The TOT00 and TOT01 pins cannot be used.
The TT0CCR1 register is not used in the external event count mode.
Figure 9-14. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer registerTT0CE bit
TT0CCR0 register
Edge
detector
Note
Clear
Match signal
INTTT0CC0 signal
EVTT0 pin
(external event
count input)
Note Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.