Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 474 of 1513
Aug 12, 2011
(b) Operation if TT0CCR0 register is set to FFFFH
If the TT0CCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTT0CC0 signal is generated and the output of
the TOT00 pin is inverted. At this time, an overflow interrupt request signal (INTTT0OV) is not generated, nor is
the overflow flag (TT0OPT0.TT0OVF bit) set to 1.
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
TOT00 pin output
INTTT0CC0 signal
FFFFH
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle
Interval time
10000H ×
count clock cycle