Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 473 of 1513
Aug 12, 2011
(2) Interval timer mode operation timing
(a) Operation if TT0CCR0 register is set to 0000H
If the TT0CCR0 register is set to 0000H, the INTTT0CC0 signal is generated at each count clock, and the
output of the TOT00 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TT0CE bit
TT0CCR0 register
TOT00 pin output
INTTT0CC0 signal
0000H
Interval time
Count clock cycle
Interval time
Count clock cycle
Interval time
Count clock cycle
FFFFH 0000H 0000H 0000H 0000H