Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 472 of 1513
Aug 12, 2011
(1) Interval timer mode operation flow
Figure 9-10. Software Processing Flow in Interval Timer Mode
TT0CE bit = 1
TT0CE bit = 0
Register initial setting
TT0CTL0 register
(TT0CKS0 to TT0CKS2 bits)
TT0CTL1 register,
TT0IOC0 register,
TT0CCR0 register
Initial setting of these registers is performed
before setting the TT0CE bit to 1.
The TT0CKS0 to TT0CKS2 bits can be
set at the same time as when counting
starts (TT0CE bit = 1).
The counter is initialized and counting is
stopped by clearing the TT0CE bit to 0.
The output level of the TOT00 pin is as
specified by the TT0IOC0 register.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
D 0
<1> <2>
D 0 D 0 D 0
FFFFH
16-bit counter
0000H
TT0CE bit
TT0CCR0 register
TOT00 pin output
INTTT0CC0 signal