Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
R01UH0042EJ0500 Rev.5.00 Page 470 of 1513
Aug 12, 2011
When the TT0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with
the count clock, and the counter starts counting. At this time, the output of the TOT00 pin is inverted. Additionally, the set
value of the TT0CCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
to 0000H, the output of the TOT00 pin is inverted, and a compare match interrupt request signal (INTTT0CC0) is
generated.
The interval can be calculated by the following expression.
Interval = (Set value of TT0CCR0 register + 1) × Count clock cycle
Figure 9-9. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMT0 control register 0 (TT0CTL0)
0/1 0 0 0 0
TT0CTL0
Select count clock
0: Stops counting
1: Enables counting
0/1 0/1 0/1
TT0CKS2 TT0CKS1 TT0CKS0TT0CE
(b) TMT0 control register 1 (TT0CTL1)
00000
TT0CTL1
0, 0, 0, 0:
Interval timer mode
000
TT0MD2TT0MD3 TT0MD1 TT0MD0TT0EEETT0EST
(c) TMT0 I/O control register 0 (TT0IOC0)
0 0 0 0 0/1
TT0IOC0
0: Disables TOT00 pin output
1: Enables TOT00 pin output
Setting of TOT00 pin output
level before count operation
0: Low level
1: High level
0: Disables TOT01 pin output
1: Enables TOT01 pin output
Setting of TOT01 pin output
level before count operation
0: Low level
1: High level
0/1 0/1 0/1
TT0OE1 TT0OL0 TT0OE0TT0OL1